INSIDE
X Classification
S = Single Level Cell + Single Die + S/B
A = Single Level Cell + Double Die + S/B
B = Single Level Cell + Quadruple Die + S/B
F = Single Level Cell + Single Die + L/B
G = Single Level Cell + Double Die + L/B
H = Single Level Cell + Quadruple Die + L/B
M = Multi Level Cell + Single Die + S/B
O = Multi Level Cell + Double Die + S/B
P = Multi Level Cell + Quadruple Die + S/B
T = Multi Level Cell + Single Die + L/B
U = Multi Level Cell + Double Die + L/B
V = Multi Level Cell + Quadruple Die + L/B
W = Multi Level Cell + L/B
XX Bit Organization 08 = x8
16 = x16
32 = x32
XX Density
64 = 64Mbit
28 = 128Mbit
56 = 256Mbit
12 = 512Mbit
1G = 1Gbit
2G = 2Gbit
4G = 4Gbit
8G = 8Gbit
AG = 16Gbit
BG = 32Gbit
CG = 64Gbit
DG = 128Gbit
X Mode
1 = 1nCE & 1R/nB; Sequencial Row Read Enable
2 = 1nCE & 1R/nB; Sequencial Row Read Disable
4 = 2nCE & 2R/nB; Sequencial Row Read Enable
5 = 2nCE & 2R/nB; Sequencial Row Read Disable
6 = 1nCE &1R/nB; Sequencial Row Read Enable
& Auto Read Page 0
7 = 2nCE & 2R/nB; Sequencial Row Read Enable
& Auto Read Page 0
8 = 1nCE &1R/nB; Sequencial Row Read Disable & Auto Read Page 0
9 = 2nCE &2R/nB; Sequencial Row Read Disable & Auto Read Page 0
X Version
D = Dual interface; Sequential Row Read Disable
F = 4nCE & 4R/B; Sequencial Row Read Disable
M = 1st Generation
A = 2nd Generation
B = 3rd Generation
C = 4th Generation
1 = Down Density (1st)
2 = Down Density (2nd)
X Package Type
T = TSOP
V = WSOP
S = USOP
F = FBGA (63ball)
B = FBGA (107ball)
G = FBGA (149ball)
H = TBGA
L = LGA
U = ULGA
W = Wafer
C = Chip
K = KGB
D = PGD2
X Package Material Blank = Normal, Wafer, Chip, KGB
P = Lead Free
H = Halogen Free
R = Lead & Halogen Free
Blank = Wafer, Chip
C = 0°C to 70°C
X Operating
E = -25°C to 85°C
M = -30°C to 85°C
Temperature
I = -40°C to 85°C
Blank = Wafer
B = Included Bad Block
X Bad Block
S = 1 - 5 Bad Block
P = All Good Block
Tabella dei contenuti per la edizione digitale del Firmware - Gennaio 2015 / N°108