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#include "CLC_pass_through.inc" ; Confi gure CLC for falling edge.
; bsf CLC1POL,LC1POL; option to invert signal through CLC block.
;; input level test
btfss input_signal ; What is the current value of my input signal?
goto signal_low ; Low.
goto signal_high ; High.
;; ===== This is the start of my main loop
signal_high ; Signal just transitioned high.
#ifdef RISING_EDGE_DELAY ; If I have rising edge delay,
movlw RISE_EDGE_DELAY
movwf countdown_timer ; load countdown timer with rising edge delay.
rising_edge_delay_loop ; insert 'nop's' below this line to increase delay.
#ifdef MS_DELAY ; option for millisecond delay
call millisecond_delay
#endif
#ifndef MS_DELAY
decfsz countdown_timer,1 ; Has countdown timer expired?
goto rising_edge_delay_loop; no, continue delay loop
#endif
bsf output_signal ; and drive pin high.
#endif
#ifdef FALLING_EDGE_DELAY
bsf output_signal ; drive latch high
bcf CLC1CON,LC1OE ; PORT -> pin
#endif
#ifndef FALLING_EDGE_DELAY
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Tabella dei contenuti per la edizione digitale del Firmware - Luglio-Agosto 2014 / N°102/103