SKILLS
+ Skills
RISE_EDGE_DELAY equ 0x05
FALL_EDGE_DELAY equ 0x04
#defi ne MS_DELAY
;; Confi guration Fuses
__confi g _FOSC_INTOSC & _BOREN_OFF & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF
& _WRT_OFF
;; pin-out
;; 1 - RA0 - pin available for use as scope trigger.
;; 2 - VSS
;; 3 - RA1 - Data Out / CLC1
;; 4 - RA2 - Data In / CLC1IN2
;; 5 - VDD
;; 6 - MCLR
#defi ne input_signal PORTA,2
#defi ne output_signal LATA,1
; single RAM location used for countdown_timer
countdown_timer equ 0x51
;; additional RAM location required if millisecond delay is enabled.
#ifdef MS_DELAY
ms_timer equ 0x52 ; delay counter for specifying time delay in milliseconds.
#endif
org 0x00
start
bcf TRISA,0 ; RA0 output - this can be used as a scope trigger.
bcf TRISA,1 ; RA1 output
clrf ANSELA ; all pins are digital.
movlw 0x70
movwf OSCCON ; 16 MHz clock - change this value for longer delaytimes
; and to lower current consumption.
;; CLC is set up here with the following include:
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Tabella dei contenuti per la edizione digitale del Firmware - Luglio-Agosto 2014 / N°102/103